TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

16

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

interrupt control logic

The interrupt control logic is shown in Figure 10.

DR (LSR Bit 0)

THRE (LSR bit 5)

OE (LSR bit 1)

FE (LSR bit 3)

TERI (MSR Bit 2)

INTERRUPT ENABLE (MCR Bit 3)

Interrupt

Output

ERBFI (IER Bit 0)

ETBEI (IER Bit 1)

PE (LSR Bit 2)

DDSR (MSR Bit 1)

DCTS (MSR Bit 0)

ELSI (IER Bit 1)

BI (LSR Bit 4)

EDSSI (IER Bit 3)

DRLSD (MSR Bit 3)

Figure 10. Interrupt Control Logic

interrupt enable register (IER)

The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPT output signal in response

to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The

contents of this register are summarized in Table 3 and are described in the following bulleted list.