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FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
35
COPYRIGHT
©
© 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
6.2.15 FIFOL, FIFOH - FIFO Status Port Full/Empty
FIFO Status Port Full (36)
7
6
5
4
3
2
1
0
FFOL7
FFOL6
FFOL5
FFOL4
FFOL3
FFOL2
FFOL1
FFOL0
FIFO Status Port Empty (37)
7
6
5
4
3
2
1
0
FFOH7
FFOH6
FFOH5
FFOH4
FFOH3
FFOH2
FFOH1
FFOH0
Reg
Bit#
Bit Name
Description
36
7-0
FFOL7-0
FIFO Status Port Full [7:0]. Maximum number of FIFO memory
locations underrun during the VGA image (multiply by 4 to get
number of pixels corrupted). Unsigned number.
37
7-0
FFOH7-0
FIFO Status Port Empty [7:0]. Maximum number of FIFO
memory locations used during a VGA frame (multiply by 4 to get
number of pixels filled). Unsigned number.
Range: {0 : 255}
6.2.16 FFO_LAT - FIFO Latency
FIFO Latency Low (38)
7
6
5
4
3
2
1
0
FFO_LAT7
FFO_LAT6
FFO_LAT5
FFO_LAT4
FFO_LAT3
FFO_LAT2
FFO_LAT1
FFO_LAT0
FIFO Latency High High (39)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reg
Bit#
Bit Name
Description
38
7-0
FFO_LAT7-0
FIFO Latency [7:0]. Number of output clock cycles between the
initiation of VGA writes to the FIFO memory and the TV reads from
it. Multiply by 4 to get the number of 27 MHz clock delays.
Range: {0 : 255}
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