CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features

• Fully static operation

• Buffered inputs

• Common reset

• Negative edge pulsing

• Fanout (over temperature range)

– Standard outputs: 10 LSTTL loads

– Bus driver outputs: 15 LSTTL loads

• Wide operating temperature range... – 55°C to

125°C

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL

logic ICs

• HC types

– 2 V to 6 V operation

– High noise immunity: NIL = 30% of VCC at VCC =

5 V

• HCT types

– 4.5 V to 5.5 V operation

– Direct LSTTL input logic compatibility, VIL = 0.8

V (Max), VIH = 2V (Min)

– CMOS input compatibility, II ≤ 1 μA at VOL, VOH

2 Description

The ’HC4040 and ’HCT4040 are 14-stage ripple-carry

binary counters. All counter stages are controller

flipflops. The state of the stage advances one count

on the negative clock transition of each input pulse; a

high voltage level on the MR line resets all counters to

their zero state. All inputs and outputs are buffered.

Device Information

PART NUMBER

PACKAGE

(1)

BODY SIZE (NOM)

CD54HC4040

J (CDIP, 16)

24.38 mm × 6.92 mm

CD54HCT4040

J (CDIP, 16)

24.38 mm × 6.92 mm

CD74HC4040

D (SOIC, 16)

9.90 mm × 3.90 mm

N (PDIP, 16)

19.31 mm × 6.35 mm

CD74HCT4040

D (SOIC, 16)

9.90 mm × 3.90 mm

N (PDIP, 16)

19.31 mm × 6.35 mm

(1)

For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040

SCHS203E – NOVEMBER 1998 – REVISED JULY 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.