Edge Detect

Typical <10 MHz

Power Down

3-State

1

8

3

2

5

7

CLKOUT

1Y0

1Y1

1Y2

1Y3

CLKIN

PLL

25 W

25 W

25 W

25 W

25 W

B0246-01

Copyright © 2016, Texas Instruments Incorporated

8

CDCVF2505

SCAS640G – JULY 2000 – REVISED AUGUST 2016

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Product Folder Links: CDCVF2505

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Copyright © 2000–2016, Texas Instruments Incorporated

(4)

The CLKOUT pin shall not be used to drive a trace, but only for delay tuning.

9 Detailed Description

9.1 Overview

The CDCVF2505 is designed for synchronous DRAM in server systems. This makes the device ideal for

applications which require the lowest possible skew between a provided reference clock and the clock copies

generated from the internal oscillator. At the same time, the phase-locked-loop has a high enough bandwidth to

track a spread-spectrum reference clock.

9.2 Functional Block Diagram

9.3 Feature Description

The CDCVF2505 provides a single high-impedance reference input to a phase-locked-loop circuit (PLL). The

reference is directly fed to a phase comparator. The control circuit loop filter is integrated into the device. The

oscillator output is fed to a clock tree with five output buffers. One of them is used as feedback to close the loop

of the PLL circuit. (4) The feedback path is designed for lowest phase difference or skew seen between reference

input and outputs. With respect to the supported reference frequency range the seen phase difference is

negligible to the clock period. Thus the CDCVF2505 is categorized as a Zero Delay PLL.

The CDCVF2505 contains an reference clock detector. This edge detector connected to CLKIN pin automatically

powers down the PLL and tri-states the output buffers to save power, as soon as the input reference frequency

goes below the minimum operating frequency range.