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Revision 4.2

July 29, 2005

Confidential

VSC7177

Data Sheet

Thermal Specifications

Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled using

a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more information,

see the JEDEC standard.

To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described

in the JEDEC standard EIA/JESD51 series must be applied. For information about specific applications, see the

following:

EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment

Mechanisms

EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements

EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements

Moisture Sensitivity

This device is rated moisture sensitivity level 3 or better as specified in the joint IPC and JEDEC standard

IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.

Table 18. Thermal Resistances

Part Number

θ

JC

θ

0

100

200

VSC7177YI

18.2

30

28.7

27

VSC7177XYI

18.2

30

28.7

27