LM5072

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SNVS437D – MARCH 2006 – REVISED APRIL 2013

PIN DESCRIPTIONS

Pin Number

Name

Description

1

RT

PWM controller oscillator frequency programming pin.

2

SS

Soft-start programming pin.

3

VIN

Positive supply pin for the PD interface and the internal PWM controller start-up regulator.

4

RCLASS

PD classification programming pin.

5

ICL_FAUX

Inrush current limit programming pin; also the front auxiliary power enable pin.

6

DCCL

PD interface DC current limit programming pin.

7

VEE

Negative supply pin for PD interface; connected to PoE and/or front auxiliary power return path.

8

RTN

PWM controller power return; connected to the drain of the internal PD interface hot swap

MOSFET; should be externally connected to the reference ground of the PWM controller.

9

OUT

PWM controller gate driver output pin.

10

VCC

PWM controller start-up regulator output pin.

11

nPGOOD

PD interface Power Good indicator and delay timer pin; active low state indicates PoE interface is in

normal operation.

12

CS

PWM controller current sense input pin.

13

RAUX

Rear auxiliary power enable pin; can be programmed for auxiliary power dominance over PoE

power.

14

FB

PWM controller voltage feedback pin and inverting input of the internal error amplifier; connect to

ARTN to disable the error amplifier in isolated dc-dc converter applications.

15

COMP

Output of the internal error amplifier and control input to the PWM comparator. In isolated

applications, COMP is controlled by the secondary side error amplifier via an opto-coupler.

16

ARTN

PWM controller reference ground pin; should be shorted externally to the RTN pin as a single point

ground connection to improve noise immunity.

EP

Exposed metal pad on the underside of the device. It is recommended to connect this pad to a PC

Board plane connected to the VEE pin to improve heat dissipation.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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