LM8333

SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013

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Some host commands include one or more data bytes read from the LM8333. Figure 11 shows a READ_INT

command which consists of an address byte, a command byte, a second address byte, and a data byte.

The first address byte is sent with the direction bit driven low to indicate a write transaction of the command to

the LM8333. The second address byte is sent with the direction bit undriven (pulled high) to indicate a read

transaction of the data from the LM8333.

The Repeated Start condition must be repeated whenever the slave address or the direction bit is changed. In

this case, the direction bit is changed.

The data is sent from the slave to the host in the fourth byte. This byte ends with a negative acknowledgement

(NACK) to indicate the end of the data.

Figure 11. Host Read Command

WAKE-UP FROM HALT MODE

Any bus transaction initiated by the host may encounter the LM8333 device in Halt mode or busy with processing

data, such as controlling the FIFO buffer or executing interrupt service routines.

Figure 12 shows the case in which the host sends a command while the LM8333 is in Halt mode (CPU clock is

stopped). Any activity on the ACCESS.bus wakes up the LM8333, but it cannot acknowledge the first bus cycle

immediately after wake-up.

The host drives a Start condition followed by seven address bits and a R/W bit. The host then releases SDA for

one clock period, so that it can be driven by the LM8333.

If the LM8333 does not drive SDA low during the high phase of the clock period immediately after the R/W bit,

the bus cycle terminates without being acknowledged (shown as NACK in Figure 12). The host then aborts the

transaction by sending a Stop condition. After aborting the bus cycle, the host may then retry the bus cycle. On

the second attempt, the LM8333 will be able to acknowledge the slave address, because it will be in Active

mode.

Alternatively, the I2C specification allows sending a START byte (00000001), which will not be acknowledged by

any device. This byte can be used to wake up the LM8333 from Halt mode.

The LM8333 may also stall the bus transaction by pulling the SCL low, which is a valid behavior defined by the

I2C specification.

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