4

A

1

2

3

D

C

B

ROUT-

GND

LOUT+

LOUT-

E

ROUT+

VDD

SCL

SDA

HPR

MIN+

LIN

BIAS

C1N

HPL

MIN-

RIN

VSSCP

C1P

CPGND

I

2

CVDD

LM49200, LM49200TLEVAL

www.ti.com

SNAS459A – MAY 2009 – REVISED APRIL 2013

Connection Diagram

Top View

Figure 2. 20 Bump DSBGA Package

(Bump Side Down)

See Package Number YZR0020BBA

Bump Descriptions

Bump

Name

Pin Function

Type

A1

ROUT-

Right Loudspeaker Negative Output

Analog Output

A2

VDD

Power Supply

Power Input

A3

MIN+

Differential Mono Positive Input

Analog Input

A4

MIN-

Differential Mono Negative Input

Analog Input

B1

ROUT+

Right Loudspeaker Positive Output

Analog Output

B2

I2CVDD

I2C power supply

Power Input

B3

LIN

Single-ended Left Input

Analog Input

B4

RIN

Single-ended Right Input

Analog Input

C1

GND

Power Ground

Ground

C2

SCL

I2C Clock

Digital Input

C3

BIAS

Half-Supply Bias point, capacitor bypassed

Analog Output

C4

VSSCP

Negative Charge Pump Power Supply

Analog Output

D1

LOUT+

Left Loudspeaker Negative Output

Analog Output

D2

SDA

I2C Data

Digital Input

D3

CIN

Negative Terminal Charge Pump Flying Capacitor

Analog Output

D4

CIP

Positive Terminal Charge Pump Flying Capacitor

Analog Output

E1

LOUT-

Left Loudspeaker Positive Output

Analog Output

E2

HPR

Right Headphone Output

Analog Output

E3

HPL

Left Headphone Output

Analog Output

E4

CPGND

Charge Pump Ground

Ground

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2009–2013, Texas Instruments Incorporated

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