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LMH6574

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SNCS103E – NOVEMBER 2004 – REVISED AUGUST 2018

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Copyright © 2004–2018, Texas Instruments Incorporated

9 Power Supply Recommendations

9.1 Power Dissipation

The LMH6574 is optimized for maximum speed and performance in the small form factor of the standard SOIC

package. To ensure maximum output drive and highest performance, thermal shutdown is not provided.

Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power

dissipation.

Follow these steps to determine the Maximum power dissipation for the LMH6574:

1. Calculate the quiescent (no-load) power.

PAMP = ICC* (VS)

where

•

VS = V

+ - V−

(1)

2. Calculate the RMS power dissipated in the output stage:

PD (rms) = rms ((VS - VOUT) * IOUT)

where

•

VOUT is the voltage across the external load

•

IOUT is the current through the external load

•

VS is the total supply voltage

(2)

3. Calculate the total RMS power: PT = PAMP + PD.

The maximum power that the LMH6574 package can dissipate at a given temperature can be derived with the

following equation:

PMAX = (150° – TAMB)/RθJA

where

•

TAMB = Ambient temperature (°C)

•

RθJA = Thermal resistance, from junction to ambient, for a given package (°C/W)

(3)

For the SOIC package RθJA is 130 °C/W.

10 Layout

10.1 Layout Guidelines

Whenever questions about layout arise, use the evaluation board LMH730276 as a guide. To reduce parasitic

capacitances, ground and power planes should be removed near the input and output pins. For long signal paths

controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass

capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are

applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller

ceramic capacitors should be placed as close to the device as possible. In the Functional Block Diagram, the

capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion. Another way

to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.