OPA842 datasheet(12/32 Pages) TI2

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OPA842

SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010

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with RG and RM. Although this resistor will provide

SFDR is often obtained by adding this external

cancellation

for

the

bias

current,

must

capacitor, whose value is often recommended in this

well-decoupled (0.1mF in Figure 38) to filter the noise

converter data sheet. The external capacitor, in

contribution of the resistor and the input current

combination with the built-in capacitance of the ADC

noise.

input, presents a significant capacitive load to the

OPA842. Without a series isolation resistor, an

As the required RG resistor approaches 50Ω at higher

undesirable peaking or loss of stability in the amplifier

gains, the bandwidth for the circuit in Figure 38 will

may result.

far

exceed

the

bandwidth

that

same

gain

magnitude for the noninverting circuit of Figure 37.

Since the dc bias current of the CMOS ADC input is

This occurs due to the lower noise gain for the circuit

negligible, the resistor has no effect on overall gain or

of Figure 38 when the 50

Ω source impedance is

offset accuracy. Refer to the Typical Characteristic

included in the analysis. For instance, at a signal gain

graph, RS vs Capacitive Load (Figure 15) to obtain a

of –8 (RG = 50Ω, RM = open, RF = 402Ω) the noise

good starting value for the series resistor. This will

gain for the circuit of Figure 38 will be 1 + 402

Ω/(50Ω

ensure flat frequency response to the ADC input.

+ 50

Ω) = 5 due to the addition of the 50Ω source in

Increasing the external capacitor value will allow the

the noise gain equation. This gives considerable

series

resistor

reduced.

Intentionally

higher bandwidth than the noninverting gain of +8.

bandlimiting using this RC network can also be used

Using the 200MHz gain bandwidth product for the

to limit noise at the converter input.

OPA842, an inverting gain of –8 from a 50

Ω source

RG will give approximately 40MHz

VIDEO LINE DRIVING

bandwidth, whereas the noninverting gain of +8 will

Most video distribution systems are designed with

give 25MHz.

Ω series resistors to drive a matched 75Ω cable. In

order to deliver a net gain of 1 to the 75

Ω matched

BUFFERING HIGH-PERFORMANCE ADCs

load, the amplifier is typically set up for a voltage gain

To achieve full performance from a high dynamic

of +2, compensating for the 6dB attenuation of the

range ADC, considerable care must be exercised in

voltage divider formed by the series and shunt 75

the design of the input amplifier interface circuit. The

resistors at either end of the cable.

example circuit on the front page shows a typical

The circuit of Figure 37 applies to this requirement if

ac-coupled interface to a very high dynamic range

all references to 50

Ω resistors are replaced by 75Ω

converter.

This

ac-coupled

example

allows

the

values. Often, the amplifier gain is further increased

OPA842 to be operated using a signal range that

to 2.2, which recovers the additional dc loss of a

swings symmetrically around ground (0V). The 2VPP

typical long cable run. This change would require the

swing is then level-shifted through the blocking

gain resistor (RG) in Figure 37 to be reduced from

capacitor to a midscale reference level, which is

402

Ω to 335Ω. In either case, both the gain flatness

created by a well-decoupled resistive divider off the

and the differential gain/phase performance of the

converter internal reference voltages. To have a

OPA842 will provide exceptional results in video

negligible effect on the rated spurious-free dynamic

distribution applications. Differential gain and phase

range (SFDR) of the converter, the amplifier SFDR

measure the change in overall small-signal gain and

should be at least 10dB greater than the converter.

phase for the color sub-carrier frequency (3.58MHz in

The OPA842 has no effect on the rated distortion of

NTSC systems) versus changes in the large-signal

the ADS850, given its 82dB SFDR at 2VPP, 5MHz.

output level (which represents luminance information

The greater than 92dB SFDR for the OPA842 in this

in a composite video signal). The OPA842, with the

configuration will not degrade the converter.

typical 150

Ω load of a single matched video cable,

Successful application of the OPA842 for ADC driving

shows less than 0.01%/0.01° differential gain/phase

requires careful selection of the series resistor at the

errors over the standard luminance range for a

amplifier output, along with the additional shunt

positive

video

(negative

sync)

signal.

Similar

capacitor at the ADC input. To some extent, selection

performance would be observed for negative video

of this RC network will be determined empirically for

signals.

each model of the converter. Many high-performance

CMOS ADCs, like the ADS850, perform better with

the shunt capacitor at the input pin. This capacitor

provides low source impedance for the transient

currents produced by the sampling process. Improved

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