BCK

FSYNC

LRCK

DOUT

t(CKFS)

t(BCKH)

t(BCKL)

t(CKLR)

t(LRCP)

t(BCKP)

t(CKDO)

t(LRDO)

0.5 VDD

0.5 VDD

0.5 VDD

0.5 VDD

t(FSYP)

T0018-01

20

PCM1802

SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016

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Timing measurement reference level is (VIH + VIL) / 2. Rise and fall times are measured from 10% to 90% of IN to

OUT signal swing. Load capacitance of all signals is 20 pF.

Figure 26. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK Work as Outputs)

Table 8. Audio Data Interface Timing: Master Mode

PARAMETER

MIN

TYP

MAX

UNIT

t(BCKP)

BCK period

150 1 / (64 fS)

1200

ns

t(BCKH)

BCK pulse duration, high

75

600

ns

t(BCKL)

BCK pulse duration, low

75

600

ns

t(CKLR)

Delay time, BCK falling edge to LRCK valid

–10

20

ns

t(LRCP)

LRCK period

10

1 / fS

80

µs

t(CKFS)

Delay time, BCK falling edge to FSYNC valid

–10

20

ns

t(FSYP)

FSYNC period

5

1 / (2 fS)

40

µs

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

20

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

20

ns

tr

Rise time of all signals

10

ns

tf

Fall time of all signals

10

ns

7.4.2.3 Synchronization With Digital Audio System

In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does

not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK

and SCKI.

If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 fS BCK (±5 BCKs for 48 fS BCK)

during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1 / fS and digital

output is forced into BPZ code until resynchronization between LRCK and SCKI is completed.

In the case of changes less than ±5 BCKs for 64 BCK per frame (±4 BCKs for 48 BCK per frame),

resynchronization does not occur.