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15 pF

tpZL

tpLZ

VOL

VOL +0.5 V

VO

RL

499

Ω

_

+

VTEST

B

A

RE

1.2 V

Inputs

VCC

1 V

VCC

VCC/2

0 V

VCC

VCC/2

VTEST

A

RE

R

0 V

1.4 V

A

tpZH

tpHZ

0 V

VOH -0.5 V

VCC

VCC/2

0 V

VOH

VCC/2

RE

VO

R

Output

VTEST

CL

SN65MLVD201, SN65MLVD203

SN65MLVD206, SN65MLVD207

SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007

A.

All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,

duty cycle = 50 5%.

B.

RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.

C.

RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.

D.

CL is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.

Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms

Copyright © 2002–2007, Texas Instruments Incorporated

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Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207