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TAS5352ADDV Datasheet(PDF) 8 Page - Texas Instruments

Part # TAS5352ADDV
Description  TAS5352A 125-W Stereo Digital Amplifier Power Stage
PDF  35 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TAS5352ADDV Datasheet(HTML) 8 Page - Texas Instruments

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TAS5352A
SLES239A – NOVEMBER 2008 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: TAS5352A
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
6.7 Audio Specifications (Single-Ended Output)
Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%)
and a TAS5352A power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C, output filter: LDEM =
20 μH, CDEM = 1 μF (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POMAX
Maximum power output
RL = 3 Ω, 10% THD+N, clipped input signal
45
W
RL = 4 Ω, 10% THD+N, clipped input signal
35
PO
Unclipped power output
RL = 3 Ω, 0 dBFS, unclipped input signal
35
RL = 4 Ω, 0 dBFS, unclipped input signal
25
THD+N
Total harmonic distortion + noise
0 dBFS, AES17 filter
0.4%
1 W, AES17 filter
0.09%
Vn
Output integrated noise
A-weighted, AES17 filter, Auto mute
disabled
40
μV
SNR
Signal-to-noise ratio(1)
A-weighted, AES17 filter, Auto mute
disabled
109
dB
DNR
Dynamic range
A-weighted, input level = –60 dBFS, AES17
filter
109
dB
Pidle
Power dissipation due to idle losses
(IPVDD_X)
PO = 0 W, all half-bridges switching
(2)
2.6
W
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
6.8 Audio Specifications (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5352A power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C, output filter: LDEM =
10 μH, CDEM = 1 μF (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POMAX
Maximum power output
RL = 3 Ω, 10% THD+N, clipped input signal
195
W
RL = 2 Ω, 10% THD+N, clipped input signal
250
PO
Unclipped power output
RL = 3 Ω, 0 dBFS, unclipped input signal
145
RL = 2 Ω, 0 dBFS, unclipped input signal
190
THD+N
Total harmonic distortion + noise
0 dBFS, AES17 filter
0.4%
1 W, AES17 filter
0.09%
Vn
Output integrated noise
A-weighted, AES17 filter, Auto mute
disabled
50
μV
SNR
Signal-to-noise ratio(1)
A-weighted, AES17 filter, Auto mute
disabled
110
dB
DNR
Dynamic range
A-weighted, input level = –60 dBFS AES17
filter
110
dB
DC Offset
Output offset voltage
±15
mV
Pidle
Power dissipation due to idle losses
(IPVDD_X)
PO = 0 W, all half-bridges switching
(2)
2.6
W



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