PCF85263AT datasheet(96/100 Pages) NXP

96 / 100 page

PCF85263A

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Product data sheet

Rev. 4.1 — 27 November 2015

96 of 100

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

29. Tables

Table 1.

Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2.

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3.

Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 5.

RTC mode time registers . . . . . . . . . . . . . . . . . .9

Table 6.

Stop-watch mode time registers . . . . . . . . . . . 11

Table 7.

Control and function registers overview . . . . . .13

Table 8.

Time and date registers in RTC mode

(RTCM = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 9.

BCD coding . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 10. Weekday assignments . . . . . . . . . . . . . . . . . . .16

Table 11. Month assignments in BCD format . . . . . . . . . .16

Table 12. Time registers in stop-watch mode

(RTCM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 13. Alarm1 and alarm2 registers in RTC mode

coded in BCD (RTCM = 0) . . . . . . . . . . . . . . . .20

Table 14. Alarm_enables- alarm enable control register

(address 10h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 15. Alarm1 and alarm2 registers in stop-watch mode

coded in BCD (RTCM = 1) . . . . . . . . . . . . . . . .23

Table 16. Alarm_enables- alarm enable control register

(address 10h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 17. WatchDog - WatchDog control and register

(address 2Dh) bit description . . . . . . . . . . . . . .26

Table 18. WatchDog durations . . . . . . . . . . . . . . . . . . . . .26

Table 19. RAM_byte - 8-bit RAM register (address 2Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 20. TSR_mode - timestamp mode control register

(address 23h) bit description . . . . . . . . . . . . . .30

Table 21. Timestamp registers in RTC mode

(RTCM = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 22. Timestamp registers in stop-watch mode

(RTCM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 23. Offset - offset register (address 24h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 24. OFFM bit - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 25. Offset values . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 26. Correction pulses for OFFM = 0 . . . . . . . . . . . .35

Table 27. Correction pulses for OFFM = 1 . . . . . . . . . . . .36

Table 28. INTA and INTB interrupt control bits . . . . . . . . .39

Table 29. Definition of interrupt control bits . . . . . . . . . . .39

Table 30. Oscillator - oscillator control register

(address 25h) bit description . . . . . . . . . . . . . .42

Table 31. CLKIV bit - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 32. 12_24 bit - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 33. LOWJ bit - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 34. OSCD[1:0] bits - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 35. CL[1:0] bits - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 36. IO pin behavior in battery mode. . . . . . . . . . . . 44

Table 37. Battery_switch - battery switch control

(address 26h) bit description . . . . . . . . . . . . . . 44

Table 38. BSOFF bit - battery switch control (address 26h)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 39. BSRR bit - battery switch control (address 26h)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 40. BSM[1:0] bits - battery switch control (address

26h) bit description. . . . . . . . . . . . . . . . . . . . . . 45

Table 41. Battery switch-over modes. . . . . . . . . . . . . . . . 45

Table 42. BSTH - battery switch control (address 26h)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 43. Pin_IO- pin input output control register

(address 27h) bit description . . . . . . . . . . . . . . 50

Table 44. CLKPM bit - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 45. TSPULL bit - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 46. TSL bit - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 47. TSPM[1:0] bits - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 48. TSIM bit - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 49. INTAPM[1:0] bits - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 50. INTA battery mode . . . . . . . . . . . . . . . . . . . . . . 53

Table 51. Function - chip function control register

(address 28h) bit description . . . . . . . . . . . . . . 54

Table 52. 100TH bit - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 53. PI[1:0] bits - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 54. RTCM bit - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 55. RTC time counting modes . . . . . . . . . . . . . . . . 55

Table 56. STOPM bit - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 57. Oscillator stop control when STOPM = 1 . . . . . 55

Table 58. COF[2:0] bits - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 59. Clock duty cycles . . . . . . . . . . . . . . . . . . . . . . . 56

Table 60. Flags - Flag status register (address 2Bh)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 61. Reset - software reset control (address 2Fh)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 62. Registers reset values . . . . . . . . . . . . . . . . . . 59

Table 63. Stop_enable - control of STOP bit

(address 2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 64. Counter stop signal . . . . . . . . . . . . . . . . . . . . . 60

Table 65. I2C slave address byte . . . . . . . . . . . . . . . . . . . 66

Table 66. Application configuration . . . . . . . . . . . . . . . . . 68

Table 67. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 68. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 69. I2C-bus characteristics . . . . . . . . . . . . . . . . . . . 76

Table 70. SnPb eutectic process (from J-STD-020D) . . . 84

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