PCF85263ATT datasheet(40/100 Pages) NXP

40 / 100 page

PCF85263A

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Product data sheet

Rev. 4.1 — 27 November 2015

40 of 100

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

• for periodic interrupts, every time a period has elapsed

• for offset correction, every time a correction pulse is initiated

• for alarms, every time the time increments to match the alarm time

• for timestamps, every time a register updates

• for battery switch, every time the IC switches to or from battery

• for WatchDog, every time the counter reaches the end of its count

The interrupt signal goes active coincident with the triggering event. The signal is cleared

by an internal 128 Hz clock. The internal clock is asynchronous to the triggering event and

so the pulse duration has a minimum period of one 128 Hz cycle and a maximum of two

128 Hz cycles. Interrupt pulses may be shortened by clearing the flag before the end of

the pulse period.

In level mode, the interrupt signal follows the state of the flag. Only interrupts which are

enabled will affect the pin state. All enabled flags must be cleared for the interrupt signal

to be cleared.

The EMON is used only for monitoring all flags and can be read back in the minutes

8.9.2 Interrupt enable bits

The remainder of the bits in register INTA_enable (address 29h) and register

INTB_enable (address 2Ah) are used to select which interrupt data goes where. See

Figure 22 “Interrupt selection”

Fig 21. Interrupt pulse width

PCF85263ATT Datasheet(PDF) 40 Page - NXP Semiconductors