CONFIDENTIAL Rev. 3.6

March 26, 2021

ES9018K2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-

8800 • www.esstech.com

24

Register #64: Chip Status

8 bit, Read-Only Register

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

reserved

revision

chip_id

automute_status

lock_status

Bit

Mnemonic

Description

[7:6]

reserved

[5]

revision

1’b0 => revision W.

1

’b1 => revision V.

[4:2]

chip_id

3’d4 => ES9018K2M

[1]

automute_status

1

’b0 => Automute condition is inactive.

1

’b1 => Automute condition is active.

[0]

lock_status

1

’b0 => The Jitter Eliminator is not locked to an incoming signal.

1

’b1 => The Jitter Eliminator is locked to an incoming signal.

Register #65: GPIO Status

8 bit, Read-Only Register

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

reserved

gpio_I[1:0]

Bit

Mnemonic

Description

[7:2]

reserved

[1]

gpio_I[1]

Status of pin GPIO2

[0]

gpio_I[0]

Status of pin GPIO1

Register #69-66: DPLL Ratio

32 bit, Read-Only Register. Register 69 contains the MSBs, Register 66 contains the LSBs.

Bits

[31:0]

Mnemonic

dpll_num

This is a read-only 32-bit value that can be used to calculate the sample rate. The raw sample rate (FSR) can be calculated

using: FSR = (DPLL_NUM x FMCLK) / 232.

Note that the DPLL number (register 66-69) should be read from LSB to MSB as it is latched on the LSBs (register 66).

Register #93-70: Channel Status

Register 93 contains the MSBs, Register 70 contains the LSBs. Format is [191:0]

These registers allow read back of the SPDIF channel status. The status definition is different for the consumer configuration

and professional configuration. Please refer to the following two tables for details.