ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

www.ti.com

THE DIGITAL INPUT PINS

The ADC08B200 has 14 digital input pins, 6 of which are used for buffer control and 2 of which are used for PLL

control.

The PD Pin

The Power Down (PD) pin, when high, puts the ADC08B200 into a low power mode where power consumption is

significantly reduced below its operating power. Stopping the clock after raising the PD input will reduce power

consumption even more. The ADC is active and will perform normally about 2 microseconds after the PD pin is

brought low. However, the PLL, if used, requires 20 microseconds to stabilize after the PD pin is brought low.

The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is

high. The buffer contents are lost when PD is brought high.

The PDADC Pin

When the PDADC pin is high the ADC is powered down. The capture buffer is active and the data within it may

be clocked out.

This is helpful for reduction of average power consumption as the ADC can be powered down while data is being

read from the buffer. As with the PD pin, the ADC is active and will perform normally about 2 microseconds after

the PDADC pin is brought low. Again the PLL, if used, requires 20 microseconds to stabilize after the PD pin is

brought low.

The PLL remains active when the PDADC input is high to allow for faster initiation of data capture after PDADC

is lowered. Stopping the input clock when PDADC is invoked can result in a loss of PLL lock and a longer than

normal recovery time from PDADC.

The Master CLK Pin

Although the ADC08B200 is tested and its performance is ensured with a 200 MHz clock, it typically will function

well with clock frequencies as indicated in the Electrical Characteristics table.

The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving

a precise duty cycle is difficult, the ADC08B200 is designed to maintain performance over a range of duty cycles.

While it is specified and performance is ensured with a 50% clock duty cycle and 200 Msps, ADC08B200

performance is typically maintained with clock high and low times and a clock frequency range as indicated in the

electrical table. Note that clock minimum low and high times may not be simultaneously imposed.

The ADC Clock input line should be series terminated at the clock source in the characteristic impedance of that

line if the clock line is longer than

where

•

tr is the clock rise time

•

tprop is the propagation rate of the signal along the trace

(5)

Typical tprop is about 150 ps/inch (59 ps/cm) on FR-4 board material.

It is always best and advisable that one clock source pin drive a single destination pin for best signal integrity.

However, if the clock source is used to drive more than just one destination, the CLK pin should be a.c.

terminated with a series RC to ground such that the resistor value is equal to the characteristic impedance of the

clock line and the capacitor value is

where

•

tPROP is the signal propagation rate down the clock line

•

"L" is the line length

•

ZO is the characteristic impedance of the clock line

(6)

26

Submit Documentation Feedback

Copyright © 2007–2013, Texas Instruments Incorporated

Product Folder Links: ADC08B200