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APPLICATION INFORMATION

Input Capacitor (C

Output Capacitor (C

Capacitance Value

ESR Range

LP2950

,, LP2951

ADJUSTABLE MICROPOWER VOLTAGE REGULATORS

WITH SHUTDOWN

SLVS582D – APRIL 2006 – REVISED MARCH 2007

A 1-

µF (tantalum, ceramic, or aluminum) electrolytic capacitor should be placed locally at the input of the

LP2950 or LP2951 if there is, or will be, significant impedance between the ac filter capacitor and the input; for

example, if a battery is used as the input or if the ac filter capacitor is located more than 10 in away. There are

no ESR requirements for this capacitor, and the capacitance can be increased without limit.

As with most PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and an

ESR that falls within a certain range.

unity gain and, thus, has lower phase margins. Consequently, a larger capacitance is needed for stability. For

version), a minimum of 3.3

µF is recommended. C

regulator stability and transient response. Regardless of its value, the output capacitor should have a resonant

frequency less than 500 kHz.

The minimum capacitance values given above are for maximum load current of 100 mA. If the maximum

mA, then only 0.33

µF is required for C

For the LP2950, no load stability is inherent in the design — a desirable feature in CMOS circuits that are put in

standby (such as RAM keep-alive applications). If the LP2951 is used with external resistors to set the output

voltage, a minimum load current of 1

µA is recommended through the resistor divider.

The regulator control loop relies on the ESR of the output capacitor to provide a zero to add sufficient phase

margin to ensure unconditional regulator stability; this requires the closed-loop gain to intersect the open-loop

response in a region where the open-loop gain rolls off at 20 dB/decade. This ensures that the phase always is

less than 180

° (phase margin greater than 0°) at unity gain. Thus, a minimum-maximum range for the ESR must

be observed.

The upper limit of this ESR range is established by the fact that too high an ESR could result in the zero

occurring too soon, causing the gain to roll off too slowly, which, in turn allows a third pole to appear before unity

gain and introduce enough phase shift to cause instability. This typically limits the max ESR to approximately

5

Ω.

Conversely, the lower limit of the ESR is tied to the fact that too low an ESR shifts the zero too far out (past

unity gain) and, thus, allows the gain to roll off at 40 dB/decade at unity gain, with a resulting phase shift of

greater than 180

°. Typically, this limits the minimum ESR to approximately 20 mΩ to 30 mΩ.

For specific ESR requirements, see Typical Characteristics.

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