LDO

V

V

I

ESR

I

R

O

ESR

C

R

O

LOAD

VO

+

−

RESR

LESL

C

TPS75201M-EP

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SGLS325A – JANUARY 2006 – REVISED JULY 2013

ESR and Transient Response

LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors

are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is

used to support both functions.

Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are

resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the

inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any

capacitor therefore can be drawn as shown in Figure 21.

Figure 21. ESR and ESL

In most cases, the effect of inductive impedance ESL can be neglected. Therefore, the following application

focuses mainly on the parasitic resistance ESR.

Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.

Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL

In steady state (dc state condition), the load current is supplied by the LDO (solid arrow), and the voltage across

the capacitor is the same as the output voltage [V(CO) = VO]. This means no current is flowing into the CO branch.

If IO suddenly increases (transient condition), the following occurs:

•

The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 24). Therefore,

capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with

an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at

RESR. This voltage is shown as VESR in Figure 23.

•

When CO is conducting current to the load, initial voltage at the load is VO = V(CO) – VESR. Due to the

discharge of CO, the output voltage VO drops continuously until the response time, t1, of the LDO is reached

and the LDO resumes supplying the load. From this point, the output voltage starts rising again until it

reaches the regulated voltage. This period is shown as t2 in Figure 24.

Figure 23 also shows the impact of different ESRs on the output voltage. The left brackets show different levels

of ESRs, where number 1 displays the lowest and number 3 displays the highest ESR.

From the previous paragraphs, the following conclusions can be drawn:

•

The higher the ESR, the larger the droop at the beginning of load transient.

•

The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the

LDO response period.

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