1

2

4

5

6

14

15

CS

SCLK

SDO

0

0

0

D11

D10

D3

D2

13

D1

D0

16

t

d1

td2

t

h1

tconv

1/throughput

tq

td3

tw1

b

tsu1

a

7

ADS7886

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SLAS492B – SEPTEMBER 2005 – REVISED AUGUST 2016

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Copyright © 2005–2016, Texas Instruments Incorporated

(1)

3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.

(2)

With 50-pf load.

7.6 Timing Requirements

All specifications typical at TA = –40°C to 125°C, VDD = 2.35 V to 5.25 V (see Figure 1 and Figure 2) (unless otherwise

specified)

(1).

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tconv

Conversion time

ADS7866

VDD = 3 V

16 × tSCLK

ns

VDD = 5 V

16 × tSCLK

tq

Minimum quiet time needed from bus 3-state to start

of next conversion

VDD = 3 V

40

ns

VDD = 5 V

40

td1

Delay time, CS low to first data (0) out

VDD = 3 V

15

25

ns

VDD = 5 V

13

25

tsu1

Setup time, CS low to SCLK low

VDD = 3 V

10

ns

VDD = 5 V

10

td2

Delay time, SCLK falling to SDO

VDD = 3 V

15

25

ns

VDD = 5 V

13

25

th1

Hold time, SCLK falling to data valid(2)

VDD < 3 V

7

ns

VDD > 5 V

5.5

td3

Delay time, 16th SCLK falling edge to SDO 3-state

VDD = 3 V

10

25

ns

VDD = 5 V

8

20

tw1

Pulse duration, CS

VDD = 3 V

25

40

ns

VDD = 5 V

25

40

td4

Delay time, CS high to SDO 3-state

VDD = 3 V

17

30

ns

VDD = 5 V

15

25

twH

Pulse duration, SCLK high

VDD = 3 V

0.4 × tSCLK

ns

VDD = 5 V

0.4 × tSCLK

twL

Pulse duration, SCLK low

VDD = 3 V

0.4 × tSCLK

ns

VDD = 5 V

0.4 × tSCLK

Frequency, SCLK

VDD = 3 V

20

MHz

VDD = 5 V

20

td5

Delay time, second falling edge of clock and CS to

enter in power down (use min spec not to accidently

enter in power down) Figure 2

VDD = 3 V

–2

5

ns

VDD = 5 V

–2

5

td6

Delay time, CS and 10th falling edge of clock to

enter in power down (use max spec not to accidently

enter in power down) Figure 2

VDD = 3 V

2

–5

ns

VDD = 5 V

2

–5

Figure 1. Interface Timing Diagram