9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

In this application, two 4-input NAND gates are used to create an active-low SR latch as shown in Figure 9-1.

Unused inputs can be tied together or to VCC

This device is used to drive the tamper indicator LED and provide one bit of data to the system controller.

When the tamper switch outputs LOW, the output Q becomes HIGH. This output remains HIGH until the system

controller addresses the event and sends a LOW signal to the R input which returns the Q output back to LOW.

9.2 Typical Application

System

Controller

Tamper

Switch 1

R

SA

Q

R1

Tamper

Indicato r

R2

SC

Tamper

Switch 3

SB

Figure 9-1. Typical application schematic

9.2.1 Design Requirements

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Section 6.3. The supply voltage sets the

device's electrical characteristics as described in the Section 6.5.

The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the

CD74HC20 plus the maximum supply current, ICC, listed in the Section 6.5. The logic device can only source

or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the

maximum total current through GND or VCC listed in the Section 6.1.

Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear

and Logic (SLL) Packages and Devices.

CD74HC20, CD54HC20

SCHS130D – AUGUST 1997 – REVISED MAY 2021

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