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CD54HC86F Datasheet(PDF) 11 Page - Texas Instruments

Part # CD54HC86F
Description  CDx4HC86 Quadruple 2-Input XOR Gates
PDF  27 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

CD54HC86F Datasheet(HTML) 11 Page - Texas Instruments

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The CD74HC86 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates
can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Section
6.3.
Refer to the Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Section 6.5. Similarly, the ground voltage
is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as
specified by the VOL specification in the Section 6.5.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC86
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in
megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Reference
Clock
Input Clock
Out
Figure 9-2. Typical application timing diagram
www.ti.com
CD74HC86, CD54HC86
SCHS137E – AUGUST 1997 – REVISED JUNE 2021
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: CD74HC86 CD54HC86



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