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T =25 C,

V

=3.3V,

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CC

o

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High-Speed Mode

>180MHz

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VCO

forHigh-SpeedMode

f

forNormal-SpeedMode

VCO FrequencyRange

Normal-SpeedMode

<200MHz

fVCO − MHzSetPoint

Not Recommended for New Designs

CDC706

SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008...................................................................................................................................... www.ti.com

Figure 29. Period Jitter vs fVCO for Normal-Speed Mode and High-Speed Mode

The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.

Cross Coupling, Spur Suppression and Noise Rejection

Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output

stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic)

induced by output switching, leakage current, ground bouncing, power supply transients, etc.

The CDC706 is designed in a RFSiGe process technology incorporating silicon-germanium (SiGe) technology.

This process gives excellent performance in linearity, low power consumption, best-in-class noise performance

and very good isolation characteristic between the on-chip components.

The good isolation was a major criteria to use the RFSiGe process as it minimizes the coupling effect. Even if all

three PLLs are active and all outputs are on, the noise suppression is clearly above 50 dB. Figure 30 and

Figure 31 show an example of noise coupling, spur-suppression, and power supply noise rejection of CDC706.

Die respective measurement conditions are shown in Figure 30 and Figure 31.

32

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