XO

or

2LVCMOS

or

Differential

Input

CLK_IN0

CLK_IN1

InputSourceSelect

(FromEEPROM)

S0379-01

PLL Configuration and Setting

B0337-01

MUX

PLLx

PFD

Filter

VCO

VCOBypass

9-BitDividerM

1...511

12-BitDividerN

1...4095

SSC

(PLL2Only)

PLL Output

SSCOutput

(PLL2Only)

Programming

InputClock

CDCE706

SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com

Differential Clock Inputs

The CDCE706 supports differential signaling as well. In this mode, the CLK_IN0 and CLK_IN1 pins serve as

differential signal inputs and can be driven up to 200 MHz.

The minimum magnitude of the differential input voltage is 100 mV over a differential common-mode input

voltage range of 200 mV to VCC – 0.6 V. If LVDS or LVPECL signal levels are applied, ac coupling and a biasing

structure are recommended to adjust the different physical layers (see Figure 17). The capacitor removes the dc

component of the signal (common-mode voltage), whereas the ac component (voltage swing) is passed on. A

resistor pullup and/or pulldown network represents the biasing structure used to set the common-mode voltage

on the receiver side of the ac-coupling capacitor. DC coupling is also possible.

Figure 17. Differential Clock Input Circuitry

The CDCE706 includes three PLLs which are equal in function and performance, except PLL2, which in addition

supports spread-spectrum clocking (SSC) generation. Figure 18 shows the block diagram of the PLL.

Figure 18. PLL Architecture

All three PLLs are designed for easiest configuration. The user must define only the input and output frequencies

or the divider (M, N, P) setting. All other parameters, such as charge-pump current, filter components, phase

margin, or loop bandwidth are controlled and set by the device itself. This assures optimized jitter attenuation and

loop stability.

The PLLs supports normal-speed mode (80 MHz

≤ fVCO ≤ 200 MHz) and high-speed mode (180 MHz ≤ fVCO ≤

300 MHz), which can be selected by PLLxFVCO (bits [7:5] of byte 6). The speed option assures stable operation

and lowest jitter.

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