10 Power Supply Recommendations

To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is

recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close

to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated

power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments'

SN6501. For such applications, detailed power supply design and transformer selection recommendations are

available in SN6501 Transformer Driver for Isolated Power Supplies.

11 Layout

11.1 Layout Guidelines

ON-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and

surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires

the use of external transient protection devices. Because ESD and EFT transients have a wide frequency

bandwidth from approximately 3-MHz to 3-GHz, high-frequency layout techniques must be applied during PCB

design. A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 11-1).

• Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power

plane, and low-frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in2.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

• Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your

board.

• Use VCC and ground planes to provide low-inductance. High-frequency currents might follow the path of least

inductance and not necessarily the path of least resistance.

• Design the protection components into the direction of the signal path. Do not force the transient currents to

divert from the signal path to reach the protection device.

• Apply 0.1-µF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, and controller ICs

on the board.

• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to

minimize effective via-inductance.

• Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during

transient events.

• Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified

maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the

transceiver and prevent it from latching up.

• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide

varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient

blocking units (TBUs) that limit transient current to less than 1 mA.

ISO3080, ISO3082, ISO3086, ISO3088

SLOS581J – MAY 2008 – REVISED AUGUST 2023

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