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6.3.6

Preserving Boundary-Scan Functionality on DDR2 Memory Pins

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

Table 6-4. Power and Clock Domains (continued)

POWER DOMAIN

CLOCK DOMAIN

PERIPHERAL/MODULE/USAGE

System Domain

CLKDIV3

Video Port 1

System Domain

CLKDIV3

Video Port 2

System Domain

CLKDIV3

Video Port 3

System Domain

CLKDIV3

Video Port 4

System Domain

CLKDIV3

EMIFA

System Domain

CLKDIV6

HPI

System Domain

CLKDIV6

PCI

System Domain

CLKDIV6

VLYNQ

System Domain

CLKDIV6

UART

System Domain

CLKDIV6

I2C

System Domain

CLKDIV6

TIMER 0

System Domain

CLKDIV6

TIMER 1

System Domain

CLKDIV6

TIMER 2

System Domain

CLKDIV6

TIMER 3

System Domain

CLKDIV6

SPI

System Domain

CLKDIV6

McASP

System Domain

CLKDIV6

VIC

System Domain

CLKDIV6

GPIO

System Domain

CLKDIV6

PLL Controller 1

System Domain

CLKDIV6

PLL Controller 2

System Domain

CLKDIV6

Config SCR

System Domain

CLKDIV4 0

Internal EMIFA Clock

System Domain

CLKDIV4 1

Emulation and Trace

System Domain

CLKDIV4 2

VICP cop_clk/2

System Domain

CLKDIV2

VICP cop_clk

Ethernet Subsystem Domain

SerDes TXBCLK

Ethernet Subsystem

The device architecture is divided into the power and clock domains shown in Table 6-5, which further

shows the clock domains and their ratios.

Table 6-5. Clock Domain Assignment

SUBSYSTEM

CLOCK DOMAIN

DOMAIN CLOCK SOURCE

FIXED RATIO VS SYSREFCLK

FREQUENCY

DSP Subsystem

CLKDIV1

PLLC1.REFSYSCLK

Peripherals (CLKDIV3 Domain)

CLKDIV3

PLLC1.SYSCLK1

1:3

Emulation/Trace

CLKDIV4 1

PLLC1.SYSCLK2

1:4

Peripherals (CLKDIV6 Domain)

CLKDIV6

PLLC1.SYSCLK3

1:6

Internal EMIFA Clock

CLKDIV4 0

PLLC1.SYSCLK4

1:4

VICP cop_clk/2

CLKDIV4 2

PLLC1.SYSCLK5

1:4

VICP cop_clk

CLKDIV2

PLLC1.SYSCLK6

1:2

Similarly, when the DDR2 Memory Controller is not used, the VREFSSTL, RSV19, and RSV20 pins can be

connected directly to ground (VSS) to save power. However, this will prevent boundary-scan from

functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2

Memory Controller pins, VREFSSTL, RSV11, and RSV12 should be connected as follows:

• V

REFSSTL - connect to a voltage of DVDD18/2. The DVDD18/2 voltage can be generated directly from the

DVDD18 supply using two 1-kΩ resistors to form a resistor divider circuit.

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