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TMS320DM647 Datasheet(PDF) 116 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 116 Page - Texas Instruments |
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116 / 167 page  www.ti.com 6.14.2 I2C Electrical Data/Timing 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 11 9 TMS320DM647/TMS320DM648 Digital Media Processor SPRS372A – MAY 2007 – REVISED JUNE 2007 6.14.2.1 Inter-Integrated Circuits (I2C) Timing Table 6-48. Timing Requirements for I2C Timings(1) (see Figure 6-29) -720 -900 NO. STANDARD UNIT FAST MODE MODE MIN MAX MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 µs Setup time, SCL high before SDA low (for a repeated START 2 tsu(SCLH-SDAL) 4.7 0.6 µs condition) Hold time, SCL low after SDA low (for a START and a repeated 3 th(SCLL-SDAL) 4 0.6 µs START condition) 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(2) ns 7 th(SDA-SCLL) Hold time, SDA valid after SCL low 0(3) 0(3) 0.9(4) µs Pulse duration, SDA high between STOP and START 8 tw(SDAH) 4.7 1.3 µs conditions 9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (5) 300 ns 10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (5) 300 ns 11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (5) 300 ns 12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (5) 300 ns 13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs 14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns 15 Cb (5) Capacitive load for each bus line 400 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) A Fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will be the case automatically if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has to be met only if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 6-29. I2C Receive Timings Peripheral Information and Electrical Specifications 116 Submit Documentation Feedback |
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