TMS320DM647 datasheet(138/167 Pages) TI

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TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

Table 6-59. McASP Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

0x0204 021A

XBUF8

Transmit Buffer for Serializer 8

0x0204 0220

XBUF9

Transmit Buffer for Serializer 9

0x0204 0224-0x0204 027C

–

Reserved

0x0204 0280

RBUF0

Receive Buffer for Serializer 0

0x0204 0284

RBUF1

Receive Buffer for Serializer 1

0x0204 0288

RBUF2

Receive Buffer for Serializer 2

0x0204 028C

RBUF3

Receive Buffer for Serializer 3

0x0204 0290

RBUF4

Receive Buffer for Serializer 4

0x0204 0294

RBUF5

Receive Buffer for Serializer 5

0x0204 0298

RBUF6

Receive Buffer for Serializer 6

0x0204 029C

RBUF7

Receive Buffer for Serializer 7

0x0204 02A0

RBUF8

Receive Buffer for Serializer 8

0x0204 02A4

RBUF9

Receive Buffer for Serializer 9

0x0204 02A8-0x0204 3FFF

–

Reserved

Table 6-60. McASP Data Registers

HEX ADDRESS RANGE

ACRONYM

COMMENTS

(Used when RSEL or XSEL

McASP receive buffers or McASP transmit buffers via the

bits = 0 [these bits are located

01D0 1400 – 01D0 17FF

RBUF/XBUF0

Peripheral Data Bus.

in the RFMT or XFMT registers,

respectively].)

6.17.1.3 McASP Electrical Data/Timing

6.17.1.3.1 Multichannel Audio Serial Port (McASP) Timing

Table 6-61. Timing Requirements for McASP (see Figure 6-40 and Figure 6-41)(1)

-720

-900

NO.

UNIT

MIN

MAX

tc(AHCKRX)

Cycle time, AHCLKR/X

tw(AHCKRX)

Pulse duration, AHCLKR/X high or low

tc(CKRX)

Cycle time, ACLKR/X

ACLKR/X ext

tw(CKRX)

Pulse duration, ACLKR/X high or low

ACLKR/X ext

16.5

ACLKR/X int

tsu(FRX-CKRX)

Setup time, AFSR/X input valid before ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

th(CKRX-FRX)

Hold time, AFSR/X input valid after ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

tsu(AXR-CKRX)

Setup time, AXR input valid before ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

th(CKRX-AXR)

Hold time, AXR input valid after ACLKR/X latches data

ACLKR/X ext

(1)

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

Peripheral Information and Electrical Specifications

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