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ADS5231

SBAS295A – JULY 2004 – REVISED JANUARY 2007

PIN DESCRIPTIONS (continued)

NAME

PIN #

I/O

DESCRIPTION

D1_B

11

O

Data Bit 11 (D1), Channel B

D2_B

12

O

Data Bit 10 (D2), Channel B

D3_B

13

O

Data Bit 9 (D3), Channel B

D4_B

14

O

Data Bit 8 (D4), Channel B

D5_B

15

O

Data Bit 7 (D5), Channel B

D6_B

16

O

Data Bit 6 (D6), Channel B

D7_B

17

O

Data Bit 5 (D7), Channel B

D8_B

18

O

Data Bit 4 (D8), Channel B

D9_B

19

O

Data Bit 3 (D9), Channel B

D10_B

20

O

Data Bit 2 (D10), Channel B

D11_B (MSB)

21

O

Data Bit 1 (D11), Channel B

DVA

26

O

Data Valid, Channel A

DVB

22

O

Data Valid, Channel B

GND

4, 7, 23, 25, 44

Output Buffer Ground

INA

50

I

Analog Input, Channel A

IN A

51

I

Complementary Analog Input, Channel A

INB

63

I

Analog Input, Channel B

IN B

62

I

Complementary Analog Input, Channel B

Reference Select; 0 = External (Default), 1 = Internal; Force high to set for internal reference

INT/EXT

56

I

operation.

ISET

60

O

Bias Current Setting Resistor of 56.2k

Ω to Ground

When SEL = 0, MSBI (Most Significant Bit Invert)

MSBI/SEN

41

I

1 = Binary Two's Complement, 0 = Straight Offset Binary (Default)

When SEL = 1, SEN (Serial Write Enable)

When SEL = 0, OEA (Output Enable Channel A)

OEA/SCLK

42

I

0 = Enabled (Default), 1 = Tri-State

When SEL = 1, SCLK (Serial Write Clock)

OE B

6

I

Output Enable, Channel B (0 = Enabled [Default], 1 = Tri-State)

OVRA

39

O

Over-Range Indicator, Channel A

OVRB

9

O

Over-Range Indicator, Channel B

REFB

54

I/O

Bottom Reference/Bypass (2

Ω resistor in series with a 0.1µF capacitor to ground)

REFT

53

I/O

Top Reference/Bypass (2

Ω resistor in series with a 0.1µF capacitor to ground)

Serial interface select signal. Setting SEL = 0 configures pins 41, 42, and 45 as MSBI, OEA, and

STPD, respectively. With SEL = 0, the serial interface is disabled. Setting SEL = 1 enables the serial

interface and configures pins 41, 42, and 45 as SEN, SCLK, and SDATA, respectively. Serial

SEL

1

I

registers can be programmed using these three signals. When used in this mode of operation, it is

essential to provide a low-going pulse on SEL in order to reset the serial interface registers as soon

as the device is powered up. SEL therefore also has the functionality of a RESET signal.

When SEL = 0, STPD (Power-Down)

STPD/SDATA

45

I

0 = Normal Operation (Default), 1 = Enabled

When SEL = 1, SDATA (Serial Write Data)

VDRV

5, 8, 40, 43

Output Buffer Supply

12

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