REFERENCE CIRCUIT DESIGN

CLOCKING

REF

T

REF

B

I

SET

0.1

µF

2.2

µF

2

Ω

2

Ω

2.2

µF

0.1

µF

56.2k

Ω

ADS5240

ADS5240

SBAS326E – JUNE 2004 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com

and REFB externally. In this mode, the internal

reference buffer is tri-stated. Since the switching

The digital beam-forming algorithm relies heavily on

current for the four ADCs come from the externally

gain matching across all receiver channels. A typical

forced references, it is possible for the performance

system would have about 24 quad ADCs on the

to be slightly less than when the internal references

board. In such a case, it is critical to ensure that the

are used. It should be noted that in this mode, VCM

gain is matched, essentially requiring the reference

and ISET continue to be generated from the internal

voltages seen by all the ADCs to be the same.

bandgap voltage, as in the internal reference mode. It

Matching references within the four channels of a

is

therefore

important

to

ensure

that

the

chip is done by using a single internal reference

common-mode

voltage

of

the

externally

forced

voltage buffer. Trimming the reference voltages on

reference voltages matches to within 50mV of VCM.

each chip during production ensures the reference

The state of the reference voltages during various

voltages are well matched across different chips.

combinations of PD and INT/EXT is shown in

Table 1.

All bias currents required for the internal operation of

the device are set using an external resistor to

Table 1. State of Reference Voltages for Various

ground at pin ISET. Using a 56.2kΩ resistor on ISET

Combinations of PD and INT/EXT

generates an internal reference current of 20

µA. This

current is mirrored internally to generate the bias

PD

0

0

1

1

current for the internal blocks. Using a larger external

INT/EXT

0

1

0

1

resistor at ISET reduces the reference bias current and

REFT

Tri-State

1.95V

Tri-State

Tri-State

thereby scales down the device operating power.

REFB

Tri-State

0.95V

Tri-State

Tri-State

However, it is recommended that the external resistor

be within 10% of the specified value of 56.2k

Ω so

VCM

1.45V

1.45V

Tri-State(1)

Tri-State(1)

that the internal bias margins for the various blocks

(1) Weak pull-down (approximately 5k

Ω) to ground.

are proper.

Buffering the internal bandgap voltage also generates

a voltage called VCM, which is set to the midlevel of

REFT and REFB, and is accessible on a pin. It is

The four channels on the chip operate from a single

meant as a reference voltage to derive the input

ADCLK input. To ensure that the aperture delay and

common-mode in case the input is directly coupled. It

jitter are same for all the channels, a clock tree

can

also

be

used

to

derive

the

reference

network is used to generate individual sampling

common-mode voltage in the external reference

clocks to each channel. The clock paths for all the

mode.

channels are matched from the source point all the

way to the sample-and-hold amplifier. This ensures

When using the internal reference mode, a 2

Ω

that the performance and timing for all the channels

resistor should be added between the reference pins

are identical. The use of the clock tree for matching

(REFT and REFB) and the decoupling capacitor, as

introduces an aperture delay, which is defined as the

shown in Figure 15. If the device is used in the

delay between the rising edge of ADCLK and the

external reference mode, this 2

Ω resistor is not

actual instant of sampling. The aperture delays for all

required.

the channels are matched to the best possible extent.

However, a mismatch of ±20ps (±3

σ) could exist

between the aperture instants of the four ADCs within

the same chip. However, the aperture delays of

ADCs across two different chips can be several

hundred

picoseconds

apart.

Another

critical

specification is the aperture jitter that is defined as

the uncertainty of the sampling instant. The gates in

the clock path are designed to provide an rms jitter of

approximately 1ps.

Ideally, the input ADCLK should have a 50% duty

cycle. However, while routing ADCLK to different

components onboard, the duty cycle of the ADCLK

reaching the ADS5240 could deviate from 50%. A

smaller (or larger) duty cycle reduces the time

Figure 15. Internal Reference Mode

available for sample or hold phases of each circuit,

and is therefore not optimal. For this reason, the

The device also supports the use of external

internal PLL is used to generate an internal clock that

reference voltages. This mode involves forcing REFT

has 50% duty cycle. The input sampling instant,

18

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