ADS7040IDCUT datasheet(29/43 Pages) TI2

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200

400

600

800

1000

Sampling Rate (Ksps)

C030

and 1.5 nF

250

and 1.5 nF

2.5 k

and 1.5 nF

10 k

and 1.5 nF

25 k

and 1.5 nF

50 k

and 1.5 nF

ADS7040

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SBAS676C – NOVEMBER 2014 – REVISED DECEMBER 2015

Table 5 lists the acquisition time for the above two cases for a throughput of 100 kSPS. Clearly, case 2 provides

more acquisition time for the input signal to settle.

Table 5. Acquisition Time with Different SCLK Frequencies

CONVERSION TIME

ACQUISITION TIME

CASE

SCLK

tcycle

(= 8.5 × tSCLK + tSU_CSCK)

(= tcycle – tconv)

1.2 MHz

10 µs

7.233 µs

2.767 µs

12 MHz

10 µs

0.7233 µs

9.2767 µs

For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation

results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition

Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).

9.2.3.3 Application Curve

When the output impedance of the sensor increases, the time required for the input signal to settle increases and

the performance of the SAR ADC starts degrading if the input signal does not settle within the acquisition time of

the ADC. The performance of the SAR ADC can be improved by reducing the throughput to provide enough time

for the input signal to settle. Figure 46 provides the results for ENOB achieved from the ADS7040 for case 2 at

different throughputs with different input impedances at the device input.

Figure 46. ENOB (Effective Number of Bits) Achieved from the ADS7040 at Different Throughputs

Table 6 shows the results and performance summary for this 12-bit, 10-kSPS DAQ circuit application.

Table 6. Results and Performance Summary for 8-Bit, 10-kSPS DAQ Circuit for DC Sensor

Measurements

DESIGN PARAMETER

GOAL VALUE

ACHIEVED RESULT

Throughput

10 kSPS

SNR at 100 Hz

48.5 dB

49.55 dB

THD at 100 Hz

65dB

70 dB

SINAD at 100 Hz

48dB

49.5 dB

ENOB

7.5

7.93

Power

10 µW

6 µW

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