ADS7044IDCUT datasheet(30/42 Pages) TI2

30 / 42 page

ADS7044

SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015

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11 Layout

11.1 Layout Guidelines

Figure 46 shows a board layout example for the ADS7044. Use a ground plane underneath the device and

partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and

keep the analog input signals and the reference input signals away from noise sources. In Figure 46, the analog

input and reference signals are routed on the top and left side of the device while the digital connections are

routed on the bottom and right side of the device.

The power sources to the device must be clean and well-bypassed. Use 1-

μF ceramic bypass capacitors in close

proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and

DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-impedance

paths. The AVDD supply voltage for the ADS7044 also functions as a reference for the device. Place the

decoupling capacitor (CREF) for AVDD close to the device AVDD and GND pins. CREF must be connected to the

device pins with thick copper tracks, as shown in Figure 46.

The fly-wheel RC filters are placed close to the device. Among ceramic surface-mount capacitors, COG (NPO)

ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic

capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.

11.2 Layout Example

Figure 46. Example Layout

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ADS7044IDCUT Datasheet(PDF) 30 Page - Texas Instruments