List of figures

Figure 1.

Block diagram .................................................................... 2

Figure 2.

Pin connections (top view) ............................................................ 2

Figure 3.

Input offset production distribution ....................................................... 6

Figure 4.

Gain error production distribution ....................................................... 6

Figure 5.

Common-mode rejection ratio production distribution.......................................... 6

Figure 6.

Supply current vs. supply voltage ....................................................... 6

Figure 7.

Supply current vs. input common-mode ................................................... 7

Figure 8.

Supply current vs. temperature ......................................................... 7

Figure 9.

Input bias current vs. common-mode ..................................................... 7

Figure 10.

Input bias current vs. temperature ....................................................... 7

Figure 11.

Input bias current vs. input common-mode voltage VCC = 0 V .................................... 7

Figure 12.

Input bias current vs. VSENSE .......................................................... 7

Figure 13.

Input offset voltage vs. temperature...................................................... 8

Figure 14.

Input offset voltage vs. input common-mode with VCC = 5 V ..................................... 8

Figure 15.

Input offset voltage vs. input common-mode with VCC = 2.7 V.................................... 8

Figure 16.

Input offset voltage vs. supply voltage .................................................... 8

Figure 17.

Output current vs. output voltage ....................................................... 8

Figure 18.

Output current vs. temperature with VCC = 5 V .............................................. 8

Figure 19.

Output current vs. temperature with VCC = 2.7 V ............................................. 9

Figure 20.

VOH vs. temperature ................................................................ 9

Figure 21.

VOL vs. temperature ................................................................ 9

Figure 22.

Linearity vs. VSENSE ................................................................ 9

Figure 23.

Linearity vs. VSENSE and temperature .................................................... 9

Figure 24.

Gain error vs. input common-mode ...................................................... 9

Figure 25.

Gain error vs. VICM and temperature .................................................... 10

Figure 26.

Load regulation................................................................... 10

Figure 27.

Gain vs. frequency ................................................................ 10

Figure 28.

Gain vs. frequency with different capacitive load ............................................ 10

Figure 29.

Bandwidth vs. input common-mode ..................................................... 10

Figure 30.

Overshoot vs. capacitive load ......................................................... 10

Figure 31.

Small signal response .............................................................. 11

Figure 32.

Large signal response .............................................................. 11

Figure 33.

Positive settling time 0.5% ........................................................... 11

Figure 34.

Negative settling time 0.5% .......................................................... 11

Figure 35.

12 V positive common-mode step response recovery ........................................ 11

Figure 36.

12 V negative common-mode step response recovery ........................................ 11

Figure 37.

48 V positive common-mode step response recovery ........................................ 12

Figure 38.

48 V negative common-mode step response recovery ........................................ 12

Figure 39.

100 V positive common-mode step response recovery........................................ 12

Figure 40.

100 V negative common-mode step response recovery ....................................... 12

Figure 41.

PSRR vs. frequency ............................................................... 12

Figure 42.

CMRR vs. frequency ............................................................... 12

Figure 43.

Positive overvoltage recovery ......................................................... 13

Figure 44.

Negative overvoltage recovery ........................................................ 13

Figure 45.

Overvoltage recovery vs. VICM ........................................................ 13

Figure 46.

Noise vs. frequency................................................................ 13

Figure 47.

0.1 Hz to 10 Hz voltage noise ......................................................... 13

Figure 48.

Power-up time delay ............................................................... 13

Figure 49.

Output impedance vs. frequency....................................................... 14

Figure 50.

SO8 package outline ............................................................... 15

Figure 51.

TSSOP8 package outline............................................................ 16

TSC240

List of figures

DS15039 - Rev 1

page 21/22