STA382BWSTR datasheet(40/172 Pages) STMICROELECTRONICS

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I2C bus specification

STA382BWS

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Doc ID 022784 Rev 1

I2C bus specification

The STA382BWS supports the I2C protocol via the input ports SCL and SDA_IN (master to

slave) and the output port SDA_OUT (slave to master). This protocol defines any device that

sends data on to the bus as a transmitter and any device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave.

The master always starts the transfer and provides the serial clock for synchronization. The

STA382BWS is always a slave device in all of its communications. It supports up to

400 kb/sec rate (fast-mode bit rate). The STA382BWS I2C is a slave-only interface. The I2C

interface works properly only in the case that the master clock generated by the PLL has a

frequency 10 times higher compared to the frequency of the applied SCL signal.

5.1

Communication protocol

5.1.1

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition

while the clock is high is used to identify a START or STOP condition.

5.1.2

Start condition

START is identified by a high-to-low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

5.1.3

Stop condition

STOP is identified by a low-to-high transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A STOP condition terminates communication between

the STA382BWS and the bus master.

5.1.4

Data input

During the data input the STA382BWS samples the SDA signal on the rising edge of clock

SCL. For correct device operation, the SDA signal must be stable during the rising edge of

the clock and the data can change only when the SCL line is low.

5.2

Device addressing

To start communication between the master and the STA382BWS, the master must initiate

with a start condition. Following this, the master sends to the SDA line 8 bits (MSB first)

corresponding to the device select address and read or write mode.

The seven most significant bits are the device address identifiers, corresponding to the I2C

bus definition. In the STA382BWS the I2C interface has two device addresses depending on

the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode

and to 0 for write mode. After a START condition the STA382BWS identifies on the bus the

device address and if a match is found, it acknowledges the identification on SDA bus during

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STA382BWSTR Datasheet(PDF) 40 Page - STMicroelectronics

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