7 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in Recommended

Operating Conditions.

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, TI recommends 0.1 µF and if there are multiple VCC terminals, then TI recommends .01 µF or .022 µF

for each power terminal. It is okay to parallel multiple bypass capacitors to reject different frequencies of noise. A

0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power

terminal as possible for best results.

7.2 Layout

7.2.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,

functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a

triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left

unconnected because the undefined voltages at the outside connections result in undefined operational states.

All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the

input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular

unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever

makes more sense for the logic function or is more convenient.

7.2.2 Layout Example

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1Y

1A

2Y

2A

2B

GND

V

CC

4Y

4B

3Y

3B

3A

GND

V

CC

4A

1B

0.1

F

Unused

inputs tied to

VCC

Bypass capacitor

placed close to the

device

Avoid 90°

corners for

signal lines

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Unused

output left

floating

Figure 7-1. Example Layout for the CD74AC02

www.ti.com

CD54AC02, CD74AC02

SCHS304E – JANUARY 2001 – REVISED APRIL 2025

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