7 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

Recommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each

power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and

1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

7.2 Layout

7.2.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two

inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not

be left unconnected because the undefined voltages at the outside connections result in undefined operational

states. Specified in Figure 7-1 are the rules that must be observed under all circumstances. All unused inputs

of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level

that should be applied to any particular unused input depends on the function of the device. Generally they will

be tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float

outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs

section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when

disabled.

7.2.2 Layout Example

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1Y

2Y

3A

3Y

GND

V

CC

6A

6Y

5Y

4A

4Y

GND

V

CC

5A

2A

0.1

F

Unused inputs

tied to VCC

Bypass capacitor

placed close to the

device

Avoid 90°

corners for

signal lines

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Unused

output left

floating

Figure 7-1. Example Layout for the CD74AC05

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CD54AC05, CD74AC05

SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024

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