Frequency - MHz

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D003

ICC 1.8 V

ICC 2.5 V

ICC 3.3 V

SN74LVC16245A

www.ti.com

SCES062Q – DECEMBER 1995 – REVISED JUNE 2014

Typical Application (continued)

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus

contention because it can drive currents that would exceed maximum limits. The high drive will also create fast

edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions

–

Rise time and fall time specs: See (

Δt/ΔV) in the Recommended Operating Conditions table.

–

Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.

–

Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.

2. Recommend Output Conditions

–

Load currents should not exceed 25 mA per output and 50 mA total for the part.

–

Outputs should not be pulled above VCC.

10.2.3 Application Curves

Figure 5. ICC vs Frequency

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

Recommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, 0.1

μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for

each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1

μF

and a 1

μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

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