7 Detailed Description

7.1 Overview

The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage

register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and

storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial

output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both

clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

7.2 Functional Block Diagram

RCLK

OE

SRCLR

SRCLK

SER

13

12

10

11

14

D

R

15

1

Q

A

Q

B

Q

C

Q

D

R

Q

D

Q

D

Q

2

Q

D

3

Q

E

4

Q

F

5

Q

G

6

D

R

7

9

Q

H’

Q

D

Q

Q

H

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CD74HC595

SCHS353A – JANUARY 2004 – REVISED FEBRUARY 2022

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