L9396 datasheet(38/109 Pages) STMICROELECTRONICS

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Pre-drivers

L9396

38/109

DS12539 Rev 10

4.2

Pump motor pre-driver

The device can drive a pump motor through this pre-driver for external FETs. It provides pre-

driver circuitry for the motor high-side FET and the motor recirculation FET.

The PDG gate drive signal is referenced to PDS, and the pre-driver pair shall be able to float

below the logic ground voltage, while keeping full on/off control on the external FET. This is

required to prevent the FET from being partially turned on in the case of a ground offset

between ECU and motor ground, or in case of loss of ECU ground.

Similarly, the PRG gate drive signal shall be referenced to PRS, and the pre-driver pair shall

be able to float below the logic ground voltage, while keeping full on/off control on the

external recirculation FET.

The motor FET pre-drivers shall be controlled by logic level input pins PDI and PRI, with

logical operation defined as:

The state of the PDI and PRI pins can be observed via SPI.

The device is able to generate software selectable dead time between PDG and PRG

transitions, to prevent cross-conduction on the external FETs.

In order to enable either PDG or PRG the following conditions must be met:

•

the watchdog reset must not be asserted,

•

the Enable Motor FET Driver SPI bit must be set,

•

no device faults preventing PDG or PRG operation must be present.

When disabled, PDG and PRG are driven to their low states.

4.3

Pump motor diagnostics

To enable MCU diagnostics, the device provides an internal pull-up current (IPDS) on PDS

and the PDS voltage can be read by the ADC and available over SPI.

After PDG is turned on, the device monitors the rising differential voltage between PDG and

PDS. If the differential voltage does not exceed the PDG turn-on voltage threshold within the

PDG switching time, the device disables the PDG pre-driver and sets the PDG Turn-On

Fault SPI bit. The device automatically re-enables the PDG pre-driver on the next rising PDI

edge.

After PDG is turned off, the device monitors the falling differential voltage between PDG and

PDS. If the differential voltage does not drop below the PDG turn-off voltage threshold within

the PDG switching time, the device disables both the PDG and PRG pre-drivers, sets the

PDG Turn-Off Fault SPI bit and clears the Enable Motor FET Driver SPI bit. The PDG and

Table 18. Logical operation definition

PDI

PRI

PDG

PRG

High-side FET

Recirculation FET

OFF

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