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CB35000 Datasheet(PDF) 1 Page - STMicroelectronics |
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CB35000 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 16 page  CB35000 SERIES HCMOS STANDARD CELLS PRELIMINARY DATA July 1995 1/16 ® FEATURES s 0.5 micron triple layer metal HCMOS5S pro- cess featuring retrograde well technology, low resistance salicided active areas, polysi- licide gates and thin metal oxide. s 3.3 V optimized transistor with 5 V I/O inter- face capability s 2 - input NAND delay of 210 ps (typ) with fanout = 2. s Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS. s High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike sup- pression and impedance matching. s Generators to support SPRAM, DPRAM, ROM and MULT with BIST options. s Extensive embedded function library includ- ing DSP and ST micros, popular third party micros and Synopsys synthetic libraries. Table 1 Module Generator Library Cell Description SPRAM 256K bits max 16K word max 64 bit max Zero static current Tristate outputs DPRAM 128K bits max 8K word max 64 bit max Zero static current Tristate outputs ROM 2M bits max 32K word max 64 bit max Diffusion programmable Tristate outputs MULT Parallel asynchronous operation 2’s complement product 6 to 64 bits for both inputs Ripple Carry or Fast Carry Look Ahead s Fully independent power and ground config- urations for inputs, core and outputs. s I/O ring capability up to 800 pads. s Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels. s Active pull up and pull down devices. s Buskeeper I/O functions. s Oscillators for wide frequency spectrum. s Broad range of 300 SSI cells. s Low Power / Low Drive library subset. s Design For Test includes IEEE 1149.1 JTAG Boundary Scan architecture built in. s Cadence and Mentor based design system with interfaces from multiple workstations. s Broad ceramic and plastic package range. s Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts. |
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