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L9963E Datasheet(PDF) 47 Page - STMicroelectronics

Part # L9963E
Description  Automotive Multicell battery monitoring and balancing IC
PDF  184 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9963E Datasheet(HTML) 47 Page - STMicroelectronics

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Figure 16. Cell monitoring with Internal balancing
C10
S10
B10_9
C9
S9
RLPF
RLPF
C8
RLPF
RDIS
RDIS
CLPF
CLPF
L9963E
Force lines used for
balancing. Connect them as
close as possible to the cell
connector. This improves
cell voltage sensing while
balancing is ongoing, by
minimizing the voltage drop
on the sense lines while
current is being sunk
Sense lines used for cell
voltage measurement. Keep
away from noisy lines.
Recommended PCB layout
strategy is to route them
over the first layer and
shield them using the
second layer as GND plane
The on-chip MOSFETs are switched on to sink a current from the cell, thus dissipating charge on RDIS. The
affordable balancing current is restricted by the thermal relief on the current source circuits.
The maximum balance current on each cell is 200 mA. All cells can be balanced simultaneously, provided that
junction temperature doesn’t exceed the maximum operating defined in Table 5. To prevent thermal overstress,
the Die temperature diagnostic and over temperature protections are implemented.
For further information, refer to Section 6.6.1 Cell balancing with internal MOSFETs.
4.7.2
Passive cell balancing with external MOSFETs
The external balancing includes the on-board power resistors and MOSFETs driven by the Sx pins.
Figure 17. Cell monitoring with external balancing with the mixed NMOS and PMOS transistors
C10
S10
B10_9
C9
S9
RLPF
RLPF
C8
RLPF
RDRV
RDRV
CLPF
CLPF
L9963E
Force lines used for
balancing. Connect them as
close as possible to the cell
connector. This improves
cell voltage sensing while
balancing is ongoing, by
minimizing the voltage drop
on the sense lines while
current is being sunk
Sense lines used for cell
voltage measurement. Keep
away from noisy lines.
Recommended PCB layout
strategy is to route them
over the first layer and
shield them using the
second layer as GND plane
MP
RDIS
MN
RDIS
L9963E
Cell balancing
DS13636 - Rev 12
page 47/184



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