L9965T datasheet(26/62 Pages) STMICROELECTRONICS

26 / 62 page

As shown in Figure 9 below, the SPI frame from MCU is temporarily stored in the VIF port TX FIFO (depth 1) to

be transmitted to the chained device, while the incoming frames from VIF are stored in the RX FIFO (depth 32),

where they can be read by the MCU. For the communication protocol details, see Section 5.8.

Figure 9. SPI – VIF interface management

5.7.1

SPI target

The registers of both the L9965T/TS and all the L9965x devices connected by VIF on the daisy chain can be

accessed by MCU when devices are in NORMAL state, performing read/write operations on the transceiver

through SPI.

SPI port is available for communication only in NORMAL functional state. In DEEPSLEEP, CYCLIC_COUNT and

CYCLIC_WAKEUP states only NCS and SCLK pins are active to recognize the wake-up sequence.

5.7.1.1

Physical layer

The SPI target peripheral pins and settings are described below.

Table 23. SPI pins description

Function

I/O type

Notes

Active states

NCS Chip Select

Digital In

weak pullup RIN_PU

DEEPSLEEP, CYCLIC_COUNT and

CYCLIC_WAKEUP (to recognize the wake-up

sequence)

NORMAL

SDI

Serial Data Input

Digital In

weak pulldown RIN_PD(1)

NORMAL

SDO Serial Data Output Digital Out

The output buffer is connected

to VIO

NORMAL

SCLK Serial Clock

Digital In

weak pulldown RIN_PDa

DEEP_SLEEP, CYCLIC_COUNT and

CYCLIC_WAKEUP (to recognize the wake-up

sequence)

NORMAL

1. Weak pull-down resistors on SDI and SCLK pins and weak pull-up on NCS pin are always enabled to address open failures.

Table 24. SPI overview

Parameter

Description

Protocol

Out of frame

Single frame length

40 bits

Frame protection

6-bit CRC

Max. Frequency

10 MHz

CPOL

L9965T/L9965TS

Functional description

DS14987 - Rev 1

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