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SPSB100 Datasheet(PDF) 105 Page - STMicroelectronics |
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SPSB100 Datasheet(HTML) 105 Page - STMicroelectronics |
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105 / 213 page  Symbol Parameter Condition Min Typ Max Unit tVREG_UV(1) VREG undervoltage filter time 12 15 22 μs tVREG_stup(1) VREG max start-up delay time for power-good 1.6 2 2.51 ms IVREG_CCmax Short circuit output current (to GND) Current limitation in active-full power 125 260 380 mA CVREG(2) Load capacitor Ceramic 3 4.7 10 µF 1. Digital implementation guaranteed by scan test. 2. Nominal capacitor value required for stability of the regulator. Tested with 4.7 µF ceramic (±20%). The capacitor must be located close to the regulator output pin. 7.23 BIST timing The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 7.5 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 49. BIST timing Symbol Parameter Condition Min Typ Max Unit TLBIST Logical BIST execution timing Covered by scan 12.1 14.6 18.3 ms TABIST Analog BIST execution timing Covered by scan 83 100 188 μs SPSB100 Electrical characteristics DS14640 - Rev 2 page 105/213 |
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