INA159 datasheet(10/51 Pages) TI2

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7.6 Typical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

Input Stage Offset Voltage (PV)

10%

15%

20%

-50

-40

-30

-20

-10

D001

N = 1555

Mean = 4.71 µV

Std. Dev. = 7.12 µV

Figure 7-1. Typical Distribution of Input Stage Offset Voltage

Input Stage Offset Voltage Drift (PV/qC)

2.5%

7.5%

10%

12.5%

15%

17.5%

20%

22.5%

25%

-0.4

0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

D002

N = 45

Mean = 0.0357 µV/°C

Std. Dev. = 0.099 µV/°C

Figure 7-2. Typical Distribution of Input Stage Offset Voltage

Drift

Output Stage Offset Voltage (PV)

0.05

0.1

0.15

-200

200

-150

-100

-50

100

150

D003

N = 1555

Mean = –3.18 µV

Std. Dev. = 41.26 µV

Figure 7-3. Typical Distribution of Output Stage Offset Voltage

Output Stage Offset Voltage Drift (PV/qC)

10%

15%

20%

25%

30%

-5

-4

-3

-2

-1

D004

N = 45

Mean = –1.49 µV/°C Std. Dev. = 0.89 µV/°C

Figure 7-4. Typical Distribution of Output Stage Offset Voltage

Drift

Temperature (qC)

-50

-25

100

125

150

-100

-80

-60

-40

-20

100

D005

Mean

+3V

-3V

45 units, 1 wafer lot

Figure 7-5. Input Stage Offset Voltage vs Temperature

Temperature (qC)

-50

-25

100

125

150

-500

-400

-300

-200

-100

100

200

300

400

500

D051

Mean

+3V

-3V

45 units, 1 wafer lots

Figure 7-6. Output Stage Offset Voltage vs Temperature

INA819

SBOS959D – DECEMBER 2018 – REVISED APRIL 2022

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