TDA7575BPD datasheet(17/32 Pages) STMICROELECTRONICS

17 / 32 page

TDA7575B

I2C bus interface

Doc ID 14103 Rev 3

17/32

Figure 27.

Timing diagram on the I2C bus

Figure 28.

Timing acknowledge clock pulse

5.5

 capability setting

It is possible to drive 1

 load paralleling the outputs into a single channel.

In order to implement this feature, outputs are to be connected on the board as follows:

●

OUT1+ (pin 35 and pin 36) shorted to OUT2+ (pin 19 and pin 20)

●

OUT1- (pin 28 and pin 29) shorted to OUT2- (pin 26 and pin 27).

It is recommended to minimize the impedance on the board between OUT2 and the load in

order to minimize THD distortion. It is also recommended to control the maximum mismatch

impedance between VCC pins (pin 21/pin 22 respect to pin 33/pin 34) and between PWGND

pins (pin 24/pin 25 respect to pin 30/pin 31), mismatch that must not exceed a value of

20 m



With 1

 feature settled the active input is IN2 (pin 17 and pin 18), therefore IN1 pins should

be let floating.

It is possible to set the load capability acting on 1

 pin as follows:

 pin (pin 15) < 1.5 V: two channels mode (for a minimum load of 2 )

 pin (pin 15) > 2.5 V: one channel mode (for 1  load).

It is to remember that 1

Ohm

function is a hardware selection.

Therefore it is recommended to leave 1

pin floating or shorted to GND to set the two

channels mode configuration, or to short 1

 pin to V

CC to set the one channel (1)

configuration.

SCL

SDA

START

I2CBUS

STOP

D99AU1032

SCL

MSB

23789

SDA

START

ACKNOWLEDGMENT

FROM RECEIVER

D99AU1033

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