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DP83867CS Datasheet(PDF) 127 Page - Texas Instruments |
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DP83867CS Datasheet(HTML) 127 Page - Texas Instruments |
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127 / 129 page  www.ti.com EXAMPLE BOARD LAYOUT 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND 48X (0.24) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.115) TYP ( 4.1) (R0.05) TYP (0.685) TYP (1.115) TYP (0.685) TYP VQFN - 1 mm max height RGZ0048B PLASTIC QUAD FLATPACK - NO LEAD 4218795/B 02/2017 SYMM 1 12 13 24 25 36 37 48 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 49 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL |
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