INA206

x20

Load

5V Supply

V

S

OUT

CMP1 IN+

CMP2 IN–

CMP2 IN+/0.6 REF

GND

1.2V REF OUT

CMP1 OUT

CMP2 OUT

CMP2 DELAY

CMP1RESET

1.2V REF

Transparent/Reset

Latch

V < 11.2V

Load Supply

–18V to +80V

Current Shunt

Monitor Output

CMP1 IN–/0.6 REF

C

0.01 F

BYPASS

µ

V

IN+

V

IN–

R

SHUNT

R

4.7k

PULL-UP

W

R

4.7k

PULL-UP

W

Optional Delay

Capacitor

0.2 F

µ

20kW

20kW

CMP2 IN+

CMP1 IN–

1.2V

i

1mA

£

INA206, INA207, INA208

www.ti.com

SBOS360F – JUNE 2006 – REVISED NOVEMBER 2015

Feature Description (continued)

It is important to note what will happen if events occur more rapidly than the delay timeout; for example, when

the U1 output goes high (turning on I2), but returns low (turning I1 back on) prior to reaching the 0.6-V transition

for U2. The voltage at U2 +IN ramps back down at a rate determined by the value of CDELAY, and only returns to

zero if given sufficient time.

In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the

model shown in Figure 30.

8.3.5 Comparator Maximum Input Voltage Range

The maximum voltage at the comparator input for normal operation is up to (Vs) – 1.5 V. There are special

considerations when overdriving the reference inputs (pins 3 and 6). Driving either or both inputs high enough to

drive 1 mA back into the reference introduces errors into the reference. Figure 33 shows the basic input

structure. A general guideline is to limit the voltage on both inputs to a total of 20 V. The exact limit depends on

the available voltage and whether either or both inputs are subject to the large voltage. When making this

determination, consider the 20 k

Ω from each input back to the comparator. Figure 34 shows the maximum input

voltage that avoids creating a reference error when driving both inputs (an equivalent resistance back into the

reference of 10 k

Ω.

Figure 33. Limit Current Into Reference

≤ 1 mA

Figure 34. Overdriving Comparator Inputs Without Generating a Reference Error

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