TDA7385

Application hints

Doc ID 8160 Rev 6

11/17

3

Application hints

Referred to the circuit of Figure 3.

3.1

Biasing and SVR

As shown by Figure 14, all the TDA7385’s main sections, such as Inputs, Outputs AND AC-

GND (pin 16) are internally biased at half supply voltage level (Vs/2), which is derived from

the Supply Voltage Rejection (SVR) block. In this way no current flows through the internal

feedback network. The AC-GND is common to all the 4 amplifiers and represents the

connection point of all the inverting inputs.

Both individual inputs and AC-GND are connected to Vs/2 (SVR) by means of 100 k



resistors.

To ensure proper operation and high supply voltage rejection, it is of fundamental

importance to provide a good impedance matching between Inputs and AC-GROUND

terminations. This implies that C1, C2, C3, C4, C5 capacitors have to carry the same

nominal value and their tolerance should never exceed ± 10 %.

Besides its contribution to the ripple rejection, the SVR capacitor governs the turn ON/OFF

time sequence and, consequently, plays an essential role in the pop optimization during

ON/OFF transients. To conveniently serve both needs, its minimum recommended value

is 10µF.

Figure 14.

Input/output biasing

3.2

Input stage

The TDA7385’s inputs are ground-compatible and can stand very high input signals

(± 8 Vpk) without any performances degradation.

If the standard value for the input capacitors (0.1 µF) is adopted, the low frequency cut-off

will amount to 16 Hz.