I2C bus

TDA7561

18/27

Doc ID 8326 Rev 6

6.2.4

Acknowledge

The transmitter puts a resistive HIGH level on the SDA line during the acknowledge clock

pulse (see Figure 26). The receive the acknowledges has to pull-down (LOW) the SDA line

during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock

pulse.

Transmitter:

–

master (µP) when it writes an address to the TDA7561

–

slave (TDA7561) when the µP reads a data byte from TDA7561

Receiver:

–

slave (TDA7561) when the µP writes an address to the TDA7561

–

master (µP) when it reads a data byte from TDA7561

Figure 24.

Data validity on the I2C bus

Figure 25.

Timing diagram on the I2C bus

Figure 26.

Acknowledge on the I2C bus