LPC2212 datasheet(16/45 Pages) PHILIPS

16 / 45 page

LPC2212_2214_4

Product data sheet

Rev. 04 — 3 January 2008

16 of 45

NXP Semiconductors

LPC2212/2214

16/32-bit ARM microcontrollers

[1]

SSP interface available on LPC2212/01 and LPC2214/01 only.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

6.7 External memory controller

The external Static Memory Controller (SMC) is a module which provides an interface

between the system bus and external (off-chip) memory devices. It provides support for

up to four independently conﬁgurable memory banks (16 MB each with byte lane enable

control) simultaneously. Each memory bank is capable of supporting SRAM, ROM, ﬂash

EPROM, burst ROM memory, or some external I/O devices.

Each memory bank may be 8-bit, 16-bit, or 32-bit wide.

6.8 General purpose parallel I/O (GPIO) and Fast I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

parallel I/O registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.8.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.8.2 Features added with the Fast GPIO set of registers available on

LPC2212/2214/01 only

• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All Fast GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

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